1. Field of the Invention
The present invention relates to a storage controller and storage control method for controlling a storage unit that can be constructed using a plurality of memory modules.
2. Description of the Related Art
The predominant type of main memory storage used in computers today is SDRAM (Synchronous Dynamic Random Access Memory). SDRAM is characterized by high speed operation achieved by operating synchronously with a system bus clock, and is often used in the form of a DIMM (Dual In-line Memory Module). SDRAMs having a high-speed data transfer feature called the double data rate (DDR) mode, and SDRAMs featuring a DDR2 (Double Data Rate 2) mode, i.e. a speed-enhanced version of DDR-SDRAMs, have been commercially implemented.
FIG. 1 is a diagram showing by way of example a hardware configuration of a system board in a computer system. The system board comprises a central processing unit (CPU) 20, a system controller (SC) 30, a memory access controller (MAC) 40, and a main storage unit (MSU) 50.
The CPU 20 is the part that forms the core of the computer system, and processes data by decoding instructions read out from the MSU 50 via the SC 30 and MAC 40, performing an appropriate operation based on the result of the decoding.
The SC 30 controls data, as well as the order in which the CPU 20 accesses the MSU 50, and enhances the throughput of the MSU 50 by employing an interleaving scheme that allows simultaneous access to different addresses within the MSU 50. The SC 30 converts a system address, which specifies an address in the address space of the system, into a MAC address which is passed to the MAC 40.
The MAC 40 converts the MAC address into a DIMM address, and controls memory access to the MSU 50. The MAC 40 sends an address signal, control signal, chip select signal (CS), etc., to the MSU 50, and transfers a data signal (DQ), data strobe signal (DQS), etc., to and from the MSU 50. A maximum of two such MACs 40 (MAC 0 and MAC 1) can be used.
The MSU 50 comprises a maximum of two banks, BANK 0 and BANK 1. BANK 0 and BANK 1 each comprise an SDRAM-DIMM as a basic memory module unit (basic module) and an SDRAM-DIMM as an expansion memory module unit (expansion module). A maximum of two such MSUs 50 (MSU 0 and MSU 1) can be used to match the number of MACs 40.
To accomplish read/write operations to a given memory module in the MSU 50, the SC 30 converts the system address into the MAC address in accordance with the memory module mounting information, and the MAC 40 converts the MAC address into the DIMM address.
In the prior art system configuration described above, only a memory module having the same device configuration as that of the basic memory module unit can be added as an expansion module on the system board.
FIG. 2 shows the bit structure of a MAR (Memory Assign Register) incorporated in the system controller (SC) as a register for holding memory configuration information. As shown, the MAR comprises a “Physical MSU LIMIT ADD” field, a “MAC” field, a “BANK” field, and a “RAM” field.
The “Physical MSU LIMIT ADD” field indicates the physical MSU limit address. Further, as shown in the figure, the “MAC” field is a two-bit field that indicates the memory access controller (MAC) configuration. Likewise, the “BANK” field is a two-bit field that indicates the bank configuration. On the other hand, the “RAM” field, which is also a two-bit field, indicates the memory module configuration such as DIMM capacity, type of memory device, and number of devices.
The system controller (SC) 30 performs the system address to MAC address conversion based on the values set in the MAR, and activates memory access to the designated memory access controller (MAC) 40.
There are two types of memory modules which are classified according to how DDR/DDR2-SDRAM devices are used to provide the same memory capacity. The two types are called the stacked type and the non-stacked type, respectively. In the stacked type, two sets of memory devices, twice as many as in the non-stacked type, are mounted in a single memory module, and are made individually selectable from the outside via a module pin using two chip select signals (CS0/1). The non-stacked type is controlled by only one chip select signal (CS0).
Since there are two module types as described above, if it is desirable to add a memory module of a different type than that of the basic memory module unit, with the prior art MAR structure it has not been possible to control the system address to the expansion module. Therefore there has been a problem in that modules of different types cannot be mounted in a mixed manner.
In recent years, memory modules have been increasing in capacity, and under the circumstances, when a system with a large memory capacity is needed to meet customer requirements, it is advantageous in terms of cost and supply to use a stacked type rather than a non-stacked type when twice the amount of memory is required.
On the other hand, even when the stacked type is advantageous, if the unit price of memory devices decreases further, the situation may reverse and the non-stacked type may become advantageous in terms of cost and supply. Therefore, there is a need to construct a system that can accommodate both types of memory modules when hardware is commercially implemented.
In the prior art relating to the present invention, Japanese Unexamined Patent Publication No. H11-073368 discloses a memory module accommodating a plurality of different types of memory devices. On the other hand, Japanese Unexamined Patent Publication No. 2003-076603 discloses a memory control method and apparatus wherein provisions are made so that SDRAMs of different types can be selected as desired and so that the SDRAMs of different types can be used in a mixed manner. Further, Japanese Unexamined Patent Publication No. H10-091517 discloses a memory access control method that ensures proper operation even when memory modules of different types are used in a mixed manner.